Lattice Technical Notes

Technical Notes for CPLD Devices (Files are in PDF-Format)

MACHXO Family

• TN1097 - MachXO Density Migration

ispMACH 5000 MX Family

• TN1026 - ispXP Configuration Usage Guidelines
• TN1030 - Using Memory in ispXPLD 5000MX Devices
• TN1031 - Power Estimation in ispXPLD 5000MX Devices

ispMACH 4000 Family

• TN1004 - ispMACH 4000B/C Timing Model Design and Usage Guidelines
• TN1005 - ispMACH 4000B/C Application Note -- Power Consumption Description

General

• TN1000 - sysIO Usage Guidelines for Lattice Devices
• Ground Bounce
• User Electronic Signature
• ispLSI/GAL Metastability
• Latch-up and Related Design Issues
• Input Hysteresis in Lattice CPLD and FPGA Devices

• AN8001 -- Lattice ISP in Cellular Switching Stations
• AN8007 -- 24-Bit Adder Implementation in a CPLD
• AN8014 -- Adder and Subtractor Macros Using Lattice Design Tools
• AN8016 -- Building Modulo N Counters Using ispLSI Devices
• AN8021 -- Bar Code Reader
• AN8026 -- Avoid the Pitfalls of High-Speed Logic Design Article Scan
• AN8027 -- Learn the Fundamentals of Digital Filter Design
• AN8060 -- Metastability in MACH Devices
• AN8066 -- Boundary-Scan Testability with Lattice's sysIO Capability